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Features
* MPEG I/II-Layer 3 Hardwired Decoder
- Stand-alone MP3 Decoder - 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency - Separated Digital Volume Control on Left and Right Channels (Software Control Using 31 Steps) - Bass, Medium, and Treble Control (31 Steps) - Bass Boost Sound Effect - Ancillary Data Extraction - "CRC Error" and "MPEG Frame Synchronization" Indicators * Programmable Audio Output for Interfacing With Common Audio DAC - PCM Format Compatible - I2S Format Compatible * 8-bit MCU C51 Core Based (F MAX = 20 MHz) * 2304 Bytes of Internal RAM * 64K Bytes of Code Memory - Flash: AT89C51SND1C, ROM: AT83C51SND1C * 4K Bytes of Boot Flash Memory (AT89C51SND1C) - ISP: Download from USB or UART to Any External Memory Cards * USB Rev 1.1 Controller - "Full Speed" Data Transmission * Built-in PLL - MP3 Audio Clocks - USB Clock * MultiMedia CardTM Interface Compatibility * Atmel DataFlash (R) SPI Interface Compatibility * IDE/ATAPI Interface *2 Channels 10-bit ADC, 8 kHz (8-True Bit) - Battery Voltage Monitoring - Voice Recording Controlled by Software * Up to 44 bits of General-purpose I/Os: - 4-bit Interrupt Keyboard Port for a 4 x n Matrix - SmartMediaTM Software Interface * Standard Two 16-bit Timers/Counters * Hardware Watchdog Timer * Standard Full Duplex UART with Baud Rate Generator * Two Wire Interface (TWI) Master and Slave Modes Controller * SPI Master and Slave Modes Controller * Power Management - Power-on Reset - Software Programmable MCU Clock - Idle Mode, Power-down Mode * Operating Conditions: - 3V, 10%, 25 mA Typical Operating at 25C - Temperature Range: -40C to +85C * Packages - TQFP80, PLCC84 (Development Board) - Dice
Single-Chip Microcontroller with MP3 Decoder and Man-Machine Interface
AT83C51SND1C AT89C51SND1C Preliminary Summary
Description
The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoders with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash Memory.
Rev. 4106F-8051-10/02
The AT83C51SND1C includes 64K Bytes of ROM memory. The AT8xC51SND1C includes 2304 Bytes of RAM memory. The AT8xC51SND1C provides all necessary features for man machine interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
Typical Applications
* * * *
MP3 Player PDA, Camera, Mobile Phone MP3 Car Audio/Multimedia MP3 Home Audio/Multimedia MP3
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AT8xC51SND1C
Pin Descriptions
Figure 1. AT8xC51SND1C, 80-pin TQFP Package
P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VDD
AT89C51SND1C-RO (Flash) AT83C51SND1C-RO (ROM)
VDD
PVDD FILT PVSS VSS X2 X1
TST
UVDD UVSS
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS
VDD
MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS
VDD
VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3
D+ D-
VDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Figure 2. AT8xC51SND1C 84-pin PLCC Package(1)
P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
VDD
NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS
VDD
PAVDD FILT PAVSS VSS X2 NC X1
AT89C51SND1C-SR (Flash)
VDD
MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS
TST
UVDD UVSS
VDD
Note:
1. Only samples for development board.
Pin Descriptions
All AT8xC51SND1C signals are detailed by functionality in Table 1 through Table 14. Table 1. Ports Signal Description
Signal Name Type Description Port 0 P0 is an 8-bit open-drain bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS . Port 1 P1 is an 8-bit bi-directional I/O port with internal pull-ups. Alternate Function
VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC
D+ D-
VDD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
P0.7:0
I/O
AD7:0
P1.7:0
I/O
KIN3:0 SCL SDA
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Table 1. Ports Signal Description (Continued)
Signal Name P2.7:0 Type I/O Description Port 2 P2 is an 8-bit bi-directional I/O port with internal pull-ups. Alternate Function A15:8 RXD TXD P3.7:0 I/O Port 3 P3 is an 8-bit bi-directional I/O port with internal pull-ups. INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS -
P4.7:0
I/O
Port 4 P4 is an 8-bit bi-directional I/O port with internal pull-ups.
P5.3:0
I/O
Port 5 P5 is a 4-bit bi-directional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL low pass filter input FILT receives the RC network of the PLL low pass filter. Alternate Function
X1
I
-
X2
O
-
FILT
I
-
Table 3. Timer 0 and Timer 1 Signal Description
Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level on INT0. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. P3.3 P3.2 Alternate Function
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Table 3. Timer 0 and Timer 1 Signal Description (Continued)
Signal Name Type Description Timer 0 External Clock Input When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count. Alternate Function
T0
I
P3.4
T1
I
P3.5
Table 4. Audio Interface Signal Description
Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function -
SCLK
O
-
Table 5. USB Controller Signal Description
Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 k pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function
D+
I/O
-
D-
I/O
-
Table 6. MutiMediaCard Interface Signal Description
Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Command line bi-directional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line bi-directional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. Alternate Function -
MCMD
I/O
-
MDAT
I/O
-
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Table 7. UART Signal Description
Signal Name Type Description Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Alternate Function
RXD
I/O
P3.0
TXD
O
P3.1
Table 8. SPI Controller Signal Description
Signal Name Type Description SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. Alternate Function
MISO
I/O
P4.0
MOSI
I/O
P4.1
SCK
I/O
P4.2
SS
I
P4.3
Table 9. TWI Controller Signal Description
Signal Name Type Description TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. TWI Serial Data SDA is the bi-directional TWI data line. Alternate Function
SCL
I/O
P1.6
SDA
I/O
P1.7
Table 10. A/D Converter Signal Description
Signal Name AIN1:0 AREFP AREFN Type I I I Description A/D Converter Analog Inputs Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input This pin is internally connected to AVSS. Alternate Function -
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Table 11. Keypad Interface Signal Description
Signal Name Type Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. Alternate Function
KIN3:0
I
P1.3:0
Table 12. External Access Signal Description
Signal Name Type Description Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. ISP Enable Input This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. Read Signal Read signal asserted during external data memory read operation. Write Signal Write signal asserted during external data memory write operation. Alternate Function
A15:8
I/O
P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
ISP
I/O
-
RD
O
P3.7
WR
O
P3.6
Table 13. System Signal Description
Signal Name Type Description Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-down mode returns the chip to normal operation. Test Input Test mode entry signal. This pin must be set to VDD. Alternate Function
RST
I
-
TST
I
-
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Table 14. Power Signal Description
Signal Name Type PWR Description Digital Supply Voltage Connect these pins to +3V supply voltage. Circuit Ground Connect these pins to ground. Analog Supply Voltage Connect this pin to +3V supply voltage. Analog Ground Connect this pin to ground. PLL Supply voltage Connect this pin to +3V supply voltage. PLL Circuit Ground Connect this pin to ground. USB Supply Voltage Connect this pin to +3V supply voltage. USB Ground Connect this pin to ground. Alternate Function -
VDD
VSS
GND
-
AVDD AVSS
PWR
-
GND
-
PVDD PVSS
PWR
-
GND
-
UVDD UVSS
PWR
-
GND
-
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4106F-8051-10/02
Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1) Type Pins
VDD
RTST
Input
TST
VDD
Watchdog Output P Input/Output
RRST
RST
VSS
2 osc periods Latch Output
VDD VDD VDD
P1 P2 P3 Input/Output N
VSS
P1(2) P2(3) P3 P4 P53:0
VDD
P Input/Output N
VSS
P0 MCMD MDAT ISP
VDD
P Output N
VSS
ALE SCLK DCLK DOUT DSEL MCLK
D+ D-
Input/Output
D+ D-
Notes:
1. For information on resistors value, input/output levels, and drive capability, refer to the Section "DC Characteristics", page 24. 2. When the TWI controller is enabled, P1, P 2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
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AT8xC51SND1C
Block Diagram
Figure 3. AT8xC51SND1C Block Diagram
INT0 3 INT1 3 Interrupt Handler Unit Flash ROM 64K Bytes Flash Boot 4K Bytes
VDD
VSS UVDD UVSS AVDD AVSS AREF AIN1:0
TXD RXD
T0
T1
SS MISO MOSI SCK 4 4 4 4
SCL SDA
3
3
3
3
1
1
RAM 2304 Bytes
10-bit A-to-D Converter or 10-bit ADC
UART and BRG
Timers 0/1 Watchdog
SPI/DataFlash Controller
TWI Controller
C51 (X2 CORE)
8-BIT INTERNAL BUS
Clock and PLL Unit
MP3 Decoder Unit
I2S / PCM Audio Interface
USB Controller
MMC Interface
Keyboard Interface
I/O Ports IDE Interface
1
FILT X1 X2 RST
ISP
ALE
DOUT DCLK DSEL SCLK
D+
D-
MCLK MDAT MCMD
KIN3:0
P0-P5
Note: 1 Alternate function of Port 1 3 Alternate function of Port 3 4 Alternate function of Port 4
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Application Information
Figure 4. AT8xC51SND1C Typical Application with On-board Atmel DataFlash and TWI LCD
LCD Battery
Ref.
VDD
P1.6/SCL P1.7/SDA
AVDD
VREFP
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 X1 X2
VREFN
AIN1
AIN0
RST
MCLK MDAT MCMD
MMC1 MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P4.2/SCK
P4.0/SI
DOUT DCLK DSEL SCLK
FILT PVSS P4n
P4.1/SO
DataFlash Memories
Audio DAC
Figure 5. AT8xC51SND1C Typical Application with On-board Atmel DataFlash and LCD
LCD
Battery
Ref.
VDD
P1.6/SCL P1.7/SDA
AVDD
P1.3 P0.4 P0.5 P0.6 P0.7
AIN1
AIN0
VREFP
VREFN
RST
AVSS
P1.4
P1.5
VSS
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 X1 X2
MCLK MDAT MCMD
MMC1 MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P4.2/SCK
P4.0/SI
DOUT DCLK DSEL SCLK
FILT P4.n PVSS
P4.1/SO
DataFlash Memories
Audio DAC
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AVSS
P1.4
P1.5
VSS
AT8xC51SND1C
Figure 6. AT8xC51SND1C Typical Application with On-board SSFDC Flash
LCD
Battery
Ref.
VDD
AVDD
P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 X1 X2
VREFN
AIN1
AIN0
VREFP
RST
MMC1
MCLK MDAT MCMD
MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P3.6/WR
DOUT DCLK DSEL SCLK
FILT P2 PVSS P0
P3.7/RD
Audio DAC SSFDC Memories or SmartMedia Cards
SmartMedia
Figure 7. AT8xC51SND1C Typical Application with IDE CD-ROM Drive
LCD
Battery
Ref.
VDD
P1.6/SCL P1.7/SDA
AVDD
P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7
VREFN
AIN1
AIN0
VREFP
RST
AVSS
P3.4
P3.5
VSS
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 X1 X2 P3.6/WR FILT P2 PVSS P0
MMC1
MCLK MDAT MCMD
MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P3.7/RD
DOUT DCLK DSEL SCLK
Audio DAC IDE CD-ROM
AVSS
P3.4
P3.5
VSS
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Address Spaces
The AT8xC51SND1C derivatives implement four different address spaces: * * * * Program/Code Memory Boot Memory Data Memory Special Function Registers (SFRs)
Code Memory
The AT89C51SND1C and AT83C51SND1C implement 64K Bytes of on-chip program/code memory. The AT83C51SND1C product provides the internal program/code memory in ROM technology while the AT89C51SND1C product provides it in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C51SND1C can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tools.
Boot Memory
The AT89C51SND1C implements 4K Bytes of on-chip boot memory provided in Flash technology. This boot memory is delivered programmed with a standard bootloader software allowing In-system Programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader. The AT8xC51SND1 derivatives implement 2304 Bytes of on-chip data RAM. This memory is divided in two separate areas: * * 256 Bytes of on-chip RAM memory (standard C51 memory). 2048 Bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions).
Data Memory
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Special Function Registers
The Special Function Registers (SFRs) of the AT8xC51SND1 derivatives fall into the categories detailed in Table 16 through Table 32. The relative addresses of these SFRs are provided together with their reset values in Table 33. In this table, the bit-addressable registers are identified by Note 1.
Table 16. C51 Core SFRs
Mnemonic ACC B PSW SP DPL Add E0h F0h D0h 81h 82h Name Accumulator B Register Program Status Word Stack Pointer Data Pointer Low byte Data Pointer High byte 7 - - CY - - 6 - - AC - - 5 - - F0 - - 4 - - RS1 - - 3 - - RS0 - - 2 - - OV - - 1 - - F1 - - 0 - - P - -
DPH
83h
-
-
-
-
-
-
-
-
Table 17. System Management SFRs
Mnemonic PCON AUXR AUXR1 NVERS Add 87h 8Eh A2h Name Power Control Auxiliary Register 0 Auxiliary Register 1 7 SMOD1 - - NV7 6 SMOD0 EXT16 - NV6 5 - M0 ENBOOT NV5 4 - DPHDIS - NV4 3 GF1 XRS1 GF3 NV3 2 GF0 XRS0 0 NV2 1 PD EXTRAM - NV1 0 IDL AO DPS NV0
FBh Version Number
Table 18. PLL and System Clock SFRs
Mnemonic CKCON PLLCON PLLNDIV PLLRDIV Add 8Fh E9h Name Clock Control PLL Control 7 - R1 - R9 6 - R0 N6 R8 5 - - N5 R7 4 - - N4 R6 3 - PLLRES N3 R5 2 - - N2 R4 1 - PLLEN N1 R3 0 X2 PLOCK N0 R2
EEh PLL N Divider EFh PLL R Divider
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Table 19. Interrupt SFRs
Mnemonic IEN0 Add A8h Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control High 0 Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 7 EA 6 EAUD 5 EMP3 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
IEN1
B1h
-
EUSB
-
EKB
EADC
ESPI
EI2C
EMMC
IPH0
B7h
-
IPHAUD
IPHMP3
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
IPL0
B8h
-
IPLAUD
IPLMP3
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
IPH1
B3h
-
IPHUSB
-
IPHKB
IPHADC
IPHSPI
IPHI2C
IPHMMC
IPL1
B2h
-
IPLUSB
-
IPLKB
IPLADC
IPLSPI
IPLI2C
IPLMMC
Table 20. Port SFRs
Mnemonic P0 P1 P2 P3 P4 P5 Add 80h 90h A0h B0h Name 8-bit Port 0 8-bit Port 1 8-bit Port 2 8-bit Port 3 7 - - - - - - 6 - - - - - - 5 - - - - - - 4 - - - - - - 3 - - - - - - 2 - - - - - - 1 - - - - - - 0 - - - - - -
C0h 8-bit Port 4 D8h 4-bit Port 5
Table 21. Flash Memory SFR
Mnemonic FCON Add Name 7 FPL3 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY
D1h Flash Control
Table 22. Timer SFRs
Mnemonic TCON Add 88h Name Timer/Counter 0 and 1 Control Timer/Counter 0 and 1 Modes Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
TMOD
89h
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
TL0
8Ah
-
-
-
-
-
-
-
-
TH0
8Ch
-
-
-
-
-
-
-
-
TL1
8Bh
-
-
-
-
-
-
-
-
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Table 22. Timer SFRs (Continued)
Mnemonic TH1 Add 8Dh Name Timer/Counter 1 High Byte WatchDog Timer Reset WatchDog Timer Program 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 -
WDTRST
A6h
-
-
-
-
-
-
-
-
WDTPRG
A7h
-
-
-
-
-
WTO2
WTO1
WTO0
Table 23. MP3 Decoder SFRs
Mnemonic MP3CON MP3STA MP3STA1 MP3DAT MP3ANC MP3VOL Add Name 7 MPEN MPANC - MPD7 AND7 - 6 MPBBST MPREQ - MPD6 AND6 - 5 CRCEN ERRLAY - MPD5 AND5 - 4 MSKANC ERRSYN MPFREQ MPD4 AND4 VOL4 3 MSKREQ ERRCRC MPBREQ MPD3 AND3 VOL3 2 MSKLAY MPFS1 - MPD2 AND2 VOL2 1 MSKSYN MPFS0 - MPD1 AND1 VOL1 0 MSKCRC MPVER - MPD0 AND0 VOL0
AAh MP3 Control C8h MP3 Status AFh MP3 Status 1 ACh MP3 Data ADh MP3 Ancillary Data 9Eh MP3 Audio Volume Control Left MP3 Audio Volume Control Right MP3 Audio Bass Control MP3 Audio Medium Control MP3 Audio Treble Control
MP3VOR
9Fh
-
-
-
VOR4
VOR3
VOR2
VOR1
VOR0
MP3BAS
B4h
-
-
-
BAS4
BAS3
BAS2
BAS1
BAS0
MP3MED
B5h
-
-
-
MED4
MED3
MED2
MED1
MED0
MP3TRE MP3CLK
B6h
- -
- -
- -
TRE4 MPCD4
TRE3 MPCD3
TRE2 MPCD2
TRE1 MPCD1
TRE0 MPCD0
EBh MP3 Clock Divider
Table 24. Audio Interface SFRs
Mnemonic AUDCON0 AUDCON1 AUDSTA AUDDAT AUDCLK Add 9Ah 9Bh Name Audio Control 0 Audio Control 1 7 JUST4 SRC SREQ AUD7 - 6 JUST3 DRQEN UDRN AUD6 - 5 JUST2 MSREQ AUBUSY AUD5 - 4 JUST1 MUDRN - AUD4 AUCD4 3 JUST0 - - AUD3 AUCD3 2 POL DUP1 - AUD2 AUCD2 1 DSIZ DUP0 - AUD1 AUCD1 0 HLR AUDEN - AUD0 AUCD0
9Ch Audio Status 9Dh Audio Data ECh Audio Clock Divider
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4106F-8051-10/02
Table 25. USB Controller SFRs
Mnemonic USBCON USBADDR USBINT USBIEN Add Name 7 USBE FEN - - 6 SUSPCLK UADD6 - - 5 SDRMWUP UADD5 WUPCPU EWUPCPU 4 - UADD4 EORINT EEORINT 3 UPRSM UADD3 SOFINT ESOFINT 2 RMWUPE UADD2 - - 1 CONFG UADD1 - - 0 FADDEN UADD0 SPINT ESPINT
BCh USB Global Control C6h USB Address BDh USB Global Interrupt BEh USB Global Interrupt Enable USB Endpoint Number USB Endpoint X Control USB Endpoint X Status
UEPNUM
C7h
-
-
-
-
-
-
EPNUM1
EPNUM0
UEPCONX
D4h
EPEN
-
-
-
DTGL
EPDIR
EPTYPE1
EPTYPE0
UEPSTAX UEPRST UEPINT
CEh
DIR - -
- - -
STALLRQ - -
TXRDY - -
STLCRC EP3RST EP3INT
RXSETUP EP2RST EP2INT
RXOUT EP1RST EP1INT
TXCMP EP0RST EP0INT
D5h USB Endpoint Reset F8h USB Endpoint Interrupt USB Endpoint Interrupt Enable USB Endpoint X FIFO Data USB Endpoint X Byte Counter USB Frame Number Low USB Frame Number High
UEPIEN
C2h
-
-
-
-
EP3INTE
EP2INTE
EP1INTE
EP0INTE
UEPDATX
CFh
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
UBYCTX
E2h
-
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
UFNUML
BAh
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
UFNUMH USBCLK
BBh
- -
- -
CRCOK -
CRCERR -
- -
FNUM10 -
FNUM9 USBCD1
FNUM8 USBCD0
EAh USB Clock Divider
Table 26. MMC Controller SFRs
Mnemonic MMCON0 MMCON1 MMCON2 MMSTA MMINT MMMSK MMCMD MMDAT MMCLK Add Name 7 DRPTR BLEN3 MMCEN - MCBI MCBM MC7 MD7 MMCD7 6 DTPTR BLEN2 DCR - EORI EORM MC6 MD6 MMCD6 5 CRPTR BLEN1 CCR CBUSY EOCI EOCM MC5 MD5 MMCD5 4 CTPTR BLEN0 - CRC16S EOFI EOFM MC4 MD4 MMCD4 3 MBLOCK DATDIR - DATFS F2FI F2FM MC3 MD3 MMCD3 2 DFMT DATEN DATD1 CRC7S F1FI F1FM MC2 MD2 MMCD2 1 RFMT RESPEN DATD0 RESPFS F2EI F2EM MC1 MD1 MMCD1 0 CRCDIS CMDEN FLOWC CFLCK F1EI F1EM MC0 MD0 MMCD0
E4h MMC Control 0 E5h MMC Control 1 E6h MMC Control 2 DEh MMC Control and Status
E7h MMC Interrupt DFh MMC Interrupt Mask
DDh MMC Command DCh MMC Data EDh MMC Clock Divider
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AT8xC51SND1C
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AT8xC51SND1C
Table 27. IDE Interface SFR
Mnemonic DAT16H Add F9h Name High Order Data Byte 7 D15 6 D14 5 D13 4 D12 3 D11 2 D10 1 D9 0 D8
Table 28. Serial I/O Port SFRs
Mnemonic SCON SBUF SADEN SADDR BDRCON BRL Add 98h 99h Name Serial Control Serial Data Buffer 7 FE/SM0 - - - - - 6 SM1 - - - - - 5 SM2 - - - - - 4 REN - - - BRR - 3 TB8 - - - TBCK - 2 RB8 - - - RBCK - 1 TI - - - SPD - 0 RI - - - SRC -
B9h Slave Address Mask A9h Slave Address 92h 91h Baud Rate Control Baud Rate Reload
Table 29. SPI Controller SFRs
Mnemonic SPCON SPSTA SPDAT Add Name 7 SPR2 SPIF SPD7 6 SPEN WCOL SPD6 5 SSDIS - SPD5 4 MSTR MODF SPD4 3 CPOL - SPD3 2 CPHA - SPD2 1 SPR1 - SPD1 0 SPR0 - SPD0
C3h SPI Control C4h SPI Status C5h SPI Data
Table 30. TWI Controller SFRs
Mnemonic SSCON Add 93h Name Synchronous Serial Control Synchronous Serial Status Synchronous Serial Data Synchronous Serial Address 7 SSCR2 6 SSPE 5 SSSTA 4 SSSTO 3 SSI 2 SSAA 1 SSCR1 0 SSCR0
SSSTA
94h
SSC4
SSC3
SSC2
SSC1
SSC0
0
0
0
SSDAT
95h
SSD7
SSD6
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
SSADR
96h
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSGC
Table 31. Keyboard Interface SFRs
Mnemonic KBCON KBSTA Add A3h A4h Name Keyboard Control Keyboard Status 7 KINL3 KPDE 6 KINL2 - 5 KINL1 - 4 KINL0 - 3 KINM3 KINF3 2 KINM2 KINF2 1 KINM1 KINF1 0 KINM0 KINF0
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Table 32. A/D Controller SFRs
Mnemonic ADCON ADCLK ADDL ADDH Add F3h F2h F4h F5h Name ADC Control ADC Clock Divider ADC Data Low Byte ADC Data High Byte 7 - - - ADAT9 6 ADIDL - - ADAT8 5 ADEN - - ADAT7 4 ADEOC ADCD4 - ADAT6 3 ADSST ADCD3 - ADAT5 2 - ADCD2 - ADAT4 1 - ADCD1 ADAT1 ADAT3 0 ADCS ADCD0 ADAT0 ADAT2
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AT8xC51SND1C
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AT8xC51SND1C
Table 33. SFR Addresses and Reset Values
0/8 F8h UEPINT 0000 0000 B1 0000 0000 PLLCON 0000 1000 ACC1 0000 0000 P51 XXXX 1111 PSW1 0000 0000 MP3STA1 0000 0001 P41 1111 1111 IPL01 X000 0000 P31 1111 1111 IEN01 0000 0000 P21 1111 1111 SCON 0000 0000 P11 1111 1111 TCON1 0000 0000 P01 1111 1111 0/8 Reserved SBUF XXXX XXXX BRL 0000 0000 TMOD 0000 0000 SP 0000 0111 1/9 SADEN 0000 0000 IEN1 0000 0000 SADDR 0000 0000 UEPIEN 0000 0000 UFNUML 0000 0000 IPL1 0000 0000 MP3CON 0011 1111 AUXR1 XXXX 00X0 AUDCON0 0000 1000 BDRCON XXX0 0000 TL0 0000 0000 DPL 0000 0000 2/A KBCON 0000 1111 AUDCON1 1011 0010 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E SPCON 0001 0100 UFNUMH 0000 0000 IPH1 0000 0000 SPSTA 0000 0000 USBCON 0000 0000 MP3BAS 0000 0000 MP3DAT 0000 0000 KBSTA 0000 0000 AUDSTA 1100 0000 SSSTA 1111 1000 TH0 0000 0000 AUDDAT 1111 1111 SSDAT 1111 1111 TH1 0000 0000 SPDAT XXXX XXXX USBINT 0000 0000 MP3MED 0000 0000 MP3ANC 0000 0000 WDTRST XXXX XXXX MP3VOL 0000 0000 SSADR 1111 1110 AUXR X000 1101 CKCON 0000 000X5 PCON XXXX 0000 7/F FCON3 1111 00004 1/9 DAT16H XXXX XXXX ADCLK 0000 0000 USBCLK 0000 0000 UBYCTLX 0000 0000 2/A 3/B NVERS2 1000 0100 ADCON 0000 0000 MP3CLK 0000 0000 ADDL 0000 0000 AUDCLK 0000 0000 MMCON0 0000 0000 MMDAT 1111 1111 UEPCONX 0000 0000 ADDH 0000 0000 MMCLK 0000 0000 MMCON1 0000 0000 MMCMD 1111 1111 UEPRST 0000 0000 UEPSTAX 0000 0000 USBADDR 1000 0000 USBIEN 0001 0000 MP3TRE 0000 0000 IPH0 X000 0000 MP3STA1 0100 0001 WDTPRG XXXX X000 MP3VOR 0000 0000 UEPDATX 0000 0000 UEPNUM 0000 0000 PLLNDIV 0000 0000 MMCON2 0000 0000 MMSTA 0000 0000 PLLRDIV 0000 0000 MMINT 0000 0011 MMMSK 1111 1111 4/C 5/D 6/E 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h
CFh
C0h
C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Notes:
1. 2. 3. 4. 5.
SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable. NVERS reset value depends on the silicon version. FCON register is only available in AT89C51SND1C product. FCON reset value is 00h in case of reset with hardware condition. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
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Peripherals
Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an onchip oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The MP3 decoder clock is generated by dividing the PLL output clock. The audio interface sample rates are also obtained by dividing the PLL output clock. The AT8xC51SND1C implement five 8-bit ports (P0 - P4) and one 4-bit port (P5). In addition to performing general-purpose I/Os, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bi-directional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/Os and alternate functions. The AT8xC51SND1C implement the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The AT8xC51SND1C implement a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (MP3 decoder). In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about 32M bytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data. In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 kHz are supported for low bit rates applications. The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies. Additional features are supported by the AT8xC51SND1C MP3 decoder such as volume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
Ports
Timers/Counters
Watchdog Timer
MP3 Decoder
Audio Output Interface
The AT8xC51SND1C implements an audio output interface allowing the decoded audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I 2S formats and the on-chip PLL (see Section "Clock Generator System") allows connection of almost all of the commercial audio DAC families available on the market.
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AT8xC51SND1C
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AT8xC51SND1C
Universal Serial Bus Interface
The AT8xC51SND1C implement a full-speed USB Interface. It can be used for the following purposes: * * Download of MP3 encoded audio files by supporting the USB mass storage class. In-System Programming by supporting the USB firmware upgrade class.
MultiMedia Card Interface
The AT8xC51SND1C implement a MultiMedia Card (MMC) interface compliant to the V2.2 specification in MultiMedia Card mode. The MMC allows storage of MP3 encoded audio files in removable Flash memory cards that can be easily plugged to, or removed from the application. It can also be used for In-System Programming. The AT8xC51SND1C provide an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlashTM cards, Hard Disk Drive, etc. It consists of a 16-bit bi-directional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interfaces but could be used for In-System Programming using CD-ROM. The AT8xC51SND1C implement a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: * * In-System Programming. Remote control of the AT8xC51SND1C by a host.
IDE/ATAPI Interface
Serial I/O Interface
Serial Peripheral Interface
The AT8xC51SND1C implement a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: * * * Interfacing DataFlash memory and DataFlash cards for MP3 encoded audio files storage Remote control of the AT8xC51SND1C by a host In-System Programming
TWI Controller
The AT8xC51SND1C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes: * * * Connection of slave devices like LCD controller, audio DAC... Remote control of the AT8xC51SND1C by a host In-System Programming
A/D Controller
The AT8xC51SND1C implements a 2-channel 10-bit (8 true bits) analog-to-digital converter (ADC). It is provided for the following purposes: * * * Battery monitoring Voice recording Corded remote control
Keyboard Interface
The AT8xC51SND1C implement a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1.3:0 and allow exit from idle and power-down modes.
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4106F-8051-10/02
Electrical Characteristics
Absolute Maximum Rating
Storage Temperature ......................................... -65 to +150C Voltage on any other Pin to V SS
...................................... -0.3 to +4.0V
NOTE:
IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Ambient Temperature Under Bias........................ -40 to +85C
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
VDD
........................................................................................... 2.7
to 3.3V
DC Characteristics
Digital Logic Table 34. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C
Symbol VIL V IH1 VIH2 VOL1 Parameter Input Low Voltage Input High Voltage (except RST) Input High Voltage (RST) Output Low Voltage (except P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output Low Voltage (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output High Voltage (P1, P2, P3, P4 and P5) Output High Voltage (P0, P2 address mode, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) Logical 0 Input Current (P1, P2, P3, P4 and P5) Min -0.5 0.2*VDD + 0.9 0.7*VDD Typ(1) Max 0.2*VDD - 0.1 Units V V V Test Conditions
VDD VDD + 0.5
0.45
V
IOL = 1.6 mA
VOL2
0.45
V
IOL = 3.2 mA
VOH1
VDD - 0.7
V
IOH = -30 A
VOH2
VDD - 0.7
V
IOH = -3.2 mA
IIL
-50
A
VIN = 0.45V
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AT8xC51SND1C
4106F-8051-10/02
AT8xC51SND1C
Table 34. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C
Symbol Parameter Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Logic1 to 0 Transition Current (P1, P2, P3, P4 and P5) Pull-down Resistor Pin Capacitance 50 90 10 1.8 Min Typ(1) Max Units A Test Conditions 0.45 < VIN < VDD
ILI
10
ITL RRST CIO VRET IDD
-650 200
A k pF V
Vin = 2.0V
TA = 25C
VDD Data Retention Limit
Operating Current TBD
TBD
mA
12 MHz, 16 MHz, 20 MHz, 12 MHz, 16 MHz, 20 MHz,
VDD < 3.3V VDD < 3.3V VDD < 3.3V VDD < 3.3V VDD < 3.3V VDD < 3.3V
IDL IPD
Idle Mode Current
TBD
TBD
mA A
Power-down Current
TBD
TBD
VRET < VDD < 3.3V
Note:
1. Typical values are obtained using VDD = 3V and TA = 25C. They are not tested and there is no guarantee on these values.
Figure 8. IDD/I DL Versus XTAL Frequency; VDD = 2.7 to 3.3V
TBD
IDD/IDL (mA)
TBD
TBD
0
2
4
6
8
10
12
14
16
18
20
max Active mode (mA) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA)
Frequency at XTAL (MHz)
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4106F-8051-10/02
IDD, IDL and IPD Test Conditions
Figure 9. IDD Test Condition, Active Mode VDD
RST
VDD VDD
IDD
VDD
P0 (NC) Clock Signal X2 X1 VSS
VSS
TST
All other pins are unconnected
Figure 10. IDL Test Condition, Idle Mode VDD
RST VSS P0 (NC) Clock Signal X2 X1 VSS VSS All other pins are unconnected IDL
VDD
VDD
TST
Figure 11. IPD Test Condition, Power-Down Mode VDD
RST VSS P0 (NC) X2 X1 VSS VSS All other pins are unconnected MCMD MDAT IPD
VDD
VDD
TST
26
AT8xC51SND1C
4106F-8051-10/02
AT8xC51SND1C
A-to-D Converter Table 35. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C
Symbol AVDD AIDD AIPD AVIN AVREF RREF CIA Parameter Analog Supply Voltage Analog Operating Supply Current Min 2.7 Typ Max 3.3 600 Units V A A V A VDD = 3.3V AIN1:0 = 0 to AVDD A VDD = 3.3V ADEN = 0 or PD = 1 Test Conditions
Analog Standby Current Analog Input Voltage Reference Voltage AREFN AREFP AREF Input Resistance Analog Input capacitance AVSS AVSS 2.4 10
2 AVDD
AVDD 30 10
V V k pF
TA = 25C TA = 25C
Oscillator and Crystal Schematic Figure 12. Crystal Connection
X1 C1 Q C2 VSS X2
Note:
For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 36. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C
Symbol CX1 CX2 CL DL F RS CS Parameter Internal Capacitance (X1 - VSS) Internal Capacitance (X2 - VSS) Equivalent Load Capacitance (X1 - X2) Drive Level Crystal Frequency Crystal Series Resistance Crystal Shunt Capacitance Min Typ 10 10 5 50 20 40 6 Max Unit pF pF pF W MHz pF
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4106F-8051-10/02
Phase Lock Loop Schematic Figure 13. PLL Filter Connection
PFILT R C1 VSS VSS C2
Parameters
Table 37. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C
Symbol R C1 C2 Parameter Filter Resistor Filter Capacitance 1 Filter Capacitance 2 Min Typ 100 10 2.2 Max Unit nF nF
In-System Programming Schematic Figure 14. ISP Pull-down Connection
ISP RISP VSS
Parameters
Table 38. ISP Pull-Down Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C
Symbol RISP Parameter ISP Pull-down Resistor Min Typ 2.2 Max Unit k
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AT8xC51SND1C
4106F-8051-10/02
AT8xC51SND1C
AC Characteristics
External 8-bit Bus Cycles Definition of Symbols Table 39. External 8-bit Bus Cycles Timing Symbol Definitions
Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating
Timings
Test conditions: capacitive load on all pins = 50 pF. Table 40. External 8-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to RD Low RD Pulse Width RD High to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to address Float Data Hold After RD High Instruction Float after RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 0 TCLCL-25 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 Max Variable Clock X2 Mode Min 50 TCLCL -15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL+20 4.5*TCLCL-65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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4106F-8051-10/02
Table 41. External 8-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL -15 TCLCL -20 TCLCL -20 3*TCLCL -30 6*TCLCL -25 TCLCL -20 4*TCLCL -30 7*TCLCL -20 TCLCL -15 TCLCL +20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL+20 Max Unit ns ns ns ns ns ns ns ns ns ns
Waveforms
Figure 15. External 8-bit Bus Cycle - Data Read Waveforms
ALE TLHLL
TLLRL
TRLRH
TRHLH
RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D7:0 Data In TRHDZ TRHDX
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AT8xC51SND1C
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AT8xC51SND1C
Figure 16. External 8-bit Bus Cycle - Data Write Waveforms
ALE TLHLL
TLLWL
TWLWH
TWHLH
WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 TWHQX
External IDE 16-bit Bus Cycles Definition of Symbols Table 42. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating
Timings
Test conditions: capacitive load on all pins = 50 pF.
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4106F-8051-10/02
Table 43. External IDE 16-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C
Variable Clock Standard Mode Symbol Parameter TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Clock Period ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to RD Low RD Pulse Width RD High to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold after RD High Instruction Float after RD High 0 2*TCLCL -25 4*TCLCL -30 5*TCLCL -30 0 0 TCLCL -25 Min 50 2*TCLCL -15 TCLCL -20 TCLCL -20 3*TCLCL -30 6*TCLCL -25 TCLCL -20 TCLCL +20 9*TCLCL -65 2*TCLCL -30 2.5*TCLCL -30 0 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL -20 0.5*TCLCL -20 1.5*TCLCL -30 3*TCLCL -25 0.5*TCLCL -20 0.5*TCLCL+20 4.5*TCLCL -65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 44. External IDE 16-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C
Variable Clock Standard Mode Symbol Parameter TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Clock Period ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL -15 TCLCL-20 TCLCL-20 3*TCLCL -30 6*TCLCL -25 TCLCL-20 4*TCLCL -30 7*TCLCL -20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL -15 0.5*TCLCL -20 0.5*TCLCL -20 1.5*TCLCL -30 3*TCLCL -25 0.5*TCLCL -20 2*TCLCL -30 3.5*TCLCL -20 0.5*TCLCL -15 0.5*TCLCL +20 Max Unit ns ns ns ns ns ns ns ns ns ns
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AT8xC51SND1C
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AT8xC51SND1C
Waveforms Figure 17. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE TLHLL
TLLRL
TRLRH
TRHLH
RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D15:81 Data In D7:0 Data In TRHDZ TRHDX
Note:
D15:8 is written in DAT16H SFR.
Figure 18. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE TLHLL
TLLWL
TWLWH
TWHLH
WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 D15:81 Data Out TWHQX
Note:
D15:8 is the content of DAT16H SFR.
SPI Interface Definition of Symbols Table 45. SPI Interface Timing Symbol Definitions
Signals C I O Clock Data In Data Out H L V X Z Conditions High Low Valid No Longer Valid Floating
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4106F-8051-10/02
Timings
Table 46. SPI Interface Master AC Timing (2) VDD = 2.7 to 3.3V, TA = -40 to +85C
Symbol Parameter Slave Mode TCHCH TCHCX TCLCX TSLCH, TSLCL TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLSH, TCHSH TIVCL, TIVCH TCLIX, TCHIX TSLOV TSHOX TSHSL TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge SS High after Clock Edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge SS Low to Output Data Valid Output Data Hold after SS High SS High to SS Low Input Rise Time Input Fall Time Output Rise Time Output Fall Time Master Mode TCHCH TCHCX TCLCX TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge Input Data Rise Time Input Data Fall Time Output Data Rise Time Output Data Fall Time 0 2 2 50 50 4 1.6 1.6 50 50 65 TOSC TOSC TOSC ns ns ns ns s s ns ns Note
(1)
Min
Max
Unit
8 3.2 3.2 200 100 100 100 0 0 100 100 130 130
TOSC TOSC TOSC ns ns ns ns ns ns ns ns ns ns
2 2 100 100
s s ns ns
Notes:
1. Value of this parameter depends on software. 2. Test conditions: capacitive load on all pins = 100 pF
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Waveforms Figure 19. SPI Slave Waveforms (SSCPHA = 0)
SS(1) (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOV TCHOV BIT 6 TCHCH TCLCH TCLSH TCHSH
TSHSL
TCHCX
TCLCX TCHCL
TCLOX TCHOX SLAVE LSB OUT 1
TSHOX
Note:
1. Not Defined but generally the MSB of the character, which has just been received.
Figure 20. SPI Slave Waveforms (SSCPHA = 1)
SS1(1) (output) TCHCH SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) TCLCH
TCHCX
TCLCX TCHCL
TIVCH TCHIX TIVCL TCLIX MSB IN BIT 6 TCLOV TCHOV LSB IN TCLOX TCHOX LSB OUT Port Data
SI (input)
SO (output)
Port Data
MSB OUT
BIT 6
Note:
1. Not Defined but generally the LSB of the character, which has just been received.
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Figure 21. SPI Master Waveforms (SSCPHA = 0)
SS1(1) (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) TSLOV MISO (output) 1 SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCHCH TCLCH TCLSH TCHSH TSHSL
TCHCX
TCLCX TCHCL
TCHOV TCLOV BIT 6
TCHOX TCLOX SLAVE LSB OUT
TSHOX
Note:
SS handled by software using general purpose port pin.
Figure 22. SPI Master Waveforms (SSCPHA = 1)
SS1(1) (output) TCHCH SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) TCLCH
TCHCX
TCLCX TCHCL
TIVCH TCHIX TIVCL TCLIX
SI (input)
MSB IN TCLOV
BIT 6 TCLOX TCHOX BIT 6
LSB IN
SO (output)
TCHOV Port Data MSB OUT
LSB OUT
Port Data
Note:
SS handled by software using general purpose port pin.
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Two-wire Interface Timings Table 47. TWI Interface AC Timing zVDD = 2.7 to 3.3V, TA = -40 to +85C
INPUT Min Max 14*TCLCL(4) 16*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 14*TCLCL(4) 14*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s OUTPUT Min Max 4.0 s(1) 4.7 s(1) 4.0 s(1) Note(2) 0.3 s(3) 20*TCLCL(4)- TRD 1 s(1) 8*TCLCL (4) 8*TCLCL(4) - TFC 4.7 s(1) 4.0 s(1) 4.7 s(1) -(2) 0.3 s(3)
Symbol THD; STA TLOW THIGH TRC TFC TSU; DAT1 TSU; DAT2 TSU; DAT3 THD; DAT TSU; STA TSU; STO TBUF TRD TFD
Parameter Start condition hold time SCL Low Time SCL High Time SCL Rise Time SCL Fall Time Data Set-up Time SDA Set-up Time (before repeated START condition) SDA Set-up Time (before STOP condition) Data Hold Time Repeated START Set-up Time STOP condition Set-up Time Bus Free Time SDA Rise Time SDA Fall Time
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3*TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. TCLCL = TOSC = one oscillator clock period.
Waveforms Figure 23. TWI Waveforms
START or Repeated START Condition Trd SDA (INPUT/OUTPUT) TFD Trc SCL (INPUT/OUTPUT) THD;STA TLOW THIGH T ;DAT1 T DAT HD SU Tsu;DAT2 Tfc Tsu;STO Tsu;DAT3 0.7 VDD 0.3 VDD Tbuf Repeated START Condition START Condition STOP Condition TSU;STA 0.7 VDD 0.3 VDD
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MMC Interface Definition of Symbols Table 48. MMC Interface Timing Symbol Definitions
Signals C D O Clock Data In Data Out H L V X Conditions High Low Valid No Longer Valid
Timings
Table 49. MMC Interface AC Timings VDD = 2.7 to 3.3V, TA = 0 to 70C, CL 100 pF (10 Cards)
Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TDVCH TCHDX TCHOX TOVCH Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Input Data Valid to Clock High Input Data Hold after Clock High Output Data Hold after Clock High Output Data Valid to Clock High 3 3 5 5 Min 50 10 10 10 10 Max Unit ns ns ns ns ns ns ns ns ns
Waveforms
Figure 24. MMC Input-Output Waveforms
TCHCH TCHCX MCLK TCHCL TCHIX MCMD Input MDAT Input TCHOX MCMD Output MDAT Output TOVCH TCLCH TIVCH TCLCX
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Audio Interface Definition of Symbols Table 50. Audio Interface Timing Symbol Definitions
Signals C O S Clock Data Out Data Select H L V X Conditions High Low Valid No Longer Valid
Timings
Table 51. Audio Interface AC Timings VDD = 2.7 to 3.3V, TA = 0 to 70C, CL 30pF
Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TCLSV TCLOV Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Clock Low to Select Valid Clock Low to Data Valid 30 30 10 10 10 10 Min Max 325.5(1) Unit ns ns ns ns ns ns ns
Note:
32-bit format with Fs = 48 kHz.
Waveforms
Figure 25. Audio Interface Waveforms
TCHCH TCHCX DCLK TCHCL TCLSV DSEL TCLOV DDAT Right Left TCLCH TCLCX
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Analog to Digital Converter Definition of Symbols Table 52. Analog to Digital Converter Timing Symbol Definitions
Signals C E S Clock Enable (ADEN bit) Start Conversion (ADSST bit) H L Conditions High Low
Characteristics
Table 53. Analog-to-Digital Converter AC Characteristics VDD = 2.7 to 3.3V, TA = 0 to 70C
Symbol TCLCL TEHSH TSHSL DLE ILE OSE GE Parameter Clock Period Start-up Time Conversion Time Differential nonlinearity error(1)( 2) Integral nonlinearity error(1)(3) Offset error(1)(4) Gain error(1)(5) Min 1.43 4 11*TCLCL TBD Max Unit s s s LSB
TBD TBD TBD
LSB LSB %
Notes:
1. AVDD = AVREFP = 3.0 V, AVSS = AVREFN = 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 27). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 27). 4. The offset error is the absolute difference between the straight line, which fits the actual transfer curve (after removing of gain error); and the straight line, which fits the ideal transfer curve (see Figure 27). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error); and the straight line, which fits the ideal transfer curve (see Figure 27).
Waveforms Figure 26. Analog-to-Digital Converter Internal Waveforms
CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL
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Figure 27. Analog to Digital Converter Characteristics
Code Out
Offset Gain Error Error OSE GE
1023 1022 1021 1020 1019 1018 Ideal Transfer curve
7 6 5 4 3 2 1 0 0 1 LSB (ideal) Differential non-linearity Center of a Step Integral non-linearity
Example of an Actual Transfer Curve
AVIN (LSBideal)
1 Offset Error 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
Flash Memory Definition of Symbols Table 54. Flash Memory Timing Symbol Definitions
Signals S R B ISP RST FBUSY flag L V X Conditions Low Valid No Longer Valid
Timings
Table 55. Flash Memory AC Timing VDD = 2.7 to 3.3V, TA = -40 to +85C
Symbol TSVRL TRLSX TBHBL Parameter Input ISP Valid to RST Edge Input ISP Hold after RST Edge Flash Internal Busy (Programming) Time Min 50 50 10 Typ Max Unit ns ns ms
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Waveforms
Figure 28. Flash Memory - ISP Waveforms
RST TSVRL ISP1 TRLSX
Note:
ISP must be driven through a pull-down resistor (see Section "In-System Programming", page 28).
Figure 29. Flash Memory - Internal Busy Waveforms
FBUSY Bit TBHBL
External Clock Drive and Logic Level References Definition of Symbols Table 56. External Clock Timing Symbol Definitions
Signals C Clock H L X Conditions High Low No Longer Valid
Timings
Table 57. External Clock AC Timings VDD = 2.7 to 3.3V, TA= 0 to 70C
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCR Parameter Clock Period High Time Low Time Rise Time Fall Time Cyclic Ratio in X2 mode Min 50 10 10 3 3 40 60 Max Unit ns ns ns ns ns %
Waveforms
Figure 30. External Clock Waveform
TCLCH TCHCX
VDD - 0.5
0.45 V
VIH1
TCLCX TCHCL TCLCL
VIL
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Figure 31. AC Testing Input/Output Waveforms
INPUTS
DD - 0.5
OUTPUTS VIH min VIL max
0.7 VDD 0.3 VDD
0.45 V
Notes:
1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 32. Float Waveforms
VLOAD VLOAD + 0.1 V VLOAD - 0.1 V Timing Reference Points VOH - 0.1 V VOL + 0.1 V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading V OH/V OL level occurs with IOL/IOH = 20 mA.
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Ordering Information
Table 58. Ordering Information
Part Number
AT89C51SND1C-ROTIL AT83SND1Axxx(1)-ROTIL
Memory Size
64K Flash 64K ROM
Supply Voltage
3V 3V
Temperature Range
Industrial Industrial
Max Frequency
40 MHz 40 MHz
Package(2)
TQFP80 TQFP80
Packing
Tray Tray
Notes:
1. Refers to ROM code. 2. PLCC84 package only available for development board.
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Package Information
TQFP80
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PLCC84
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and DataFlash (R) are registered trademark of Atmel. MultiMedia Card (R) is a registered trademark of MultiMedia Coroporation. SmartMedia (R) is a registered trademark of Toshiba Corporation. CompactFlash TM is a trademark of CompactFlash Corporation. Other terms and product names may be the trademarks of others. Printed on recycled paper.
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